RISC-V Opcodes and Register Names
I needed this a few times during ECE411 — Computer Organization and Design at UIUC.
Opcodes are stored in the lowest 6 bits of the instructions (for 32 bit mode at least)
LUI 0110111
AUIPC 0010111
JAL 1101111
JALR 1100111
BEQ 1100011
BNE 1100011
BLT 1100011
BGE 1100011
BLTU 1100011
BGEU 1100011
LB 0000011
LH 0000011
LW 0000011
LBU 0000011
LHU 0000011
SB 0100011
SH 0100011
SW 0100011
ADDI 0010011
SLTI 0010011
SLTIU 0010011
XORI 0010011
ORI 0010011
ANDI 0010011
SLLI 0010011
SRLI 0010011
SRAI 0010011
ADD 0110011
SUB 0110011
SLL 0110011
SLT 0110011
SLTU 0110011
XOR 0110011
SRL 0110011
SRA 0110011
OR 0110011
AND 0110011
FENCE 0001111
FENCE.I 0001111
ECALL 1110011
EBREAK 1110011
CSRRW 1110011
CSRRS 1110011
CSRRC 1110011
CSRRWI 1110011
CSRRSI 1110011
CSRRCI 1110011
pg. 104 (Chapter 19) of the RISC-V Spec, version 2.2 volume 1:
Register Names
pg. 109 (Chapter 20) of the RISC-V Spec, version 2.2 volume 1:
Contains an assembly programmer's manual (or at least, a placeholder for one)
which has some useful resources such as a mapping of pseudoinstructions to
base instructions.
Register : ABI Name : Description : Saver
x0 : zero : Hard-wired zero : -
x1 : ra : Return address : Caller
x2 : sp : Stack pointer : Callee
x3 : gp : Global pointer : -
x4 : tp : Thread pointer : -
x5 : t0 : Temporary/alternate link register : Caller
x6–7 : t1–2 : Temporaries : Caller
x8 : s0/fp : Saved register/frame pointer : Callee
x9 : s1 : Saved register : Callee
x10–11 : a0–1 : Function arguments/return values : Caller
x12–17 : a2–7 : Function arguments : Caller
x18–27 : s2–11 : Saved registers : Callee
x28–31 : t3–6 : Temporaries : Caller